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Survey of Failure Analysis Techniques for Packaging – Friday 23 October 2020 @ 12:00 UK

The tenth IMAPS-UK Online Tutorial Session is “Survey of Failure Analysis Techniques for Packaging” by Greg Johnson of Zeiss Microscopy.

This is a free to join event, please log in or register below to book a place.

This is the tenth in a series of Fundamentals of Electronics Packaging Tutorials organised by IMAPS-UK (International Microelectronics, Assembly and Packaging Society) to describe various aspects of the production and assessment of micro-electronic assemblies.

This event is supported by Zeiss Microscopy. Please follow the link to subscribe to Zeiss Microscopy News

Survey of Failure Analysis Techniques for Packaging
Greg Johnson – Zeiss Microscopy

Complete understanding of packaging failures require physical characterisation of the precise element that is failing. Once a chip is exposed to the proper level, there may be several different techniques available to further isolate the failure. Given an “alphabet soup” of acronyms, the choice of the appropriate technique for fault isolation and failure analysis can be very challenging. Additional challenges are provided by the industry moving to advanced technology nodes, novel device architectures, and 3D-stackings at chip and wafer level, making it more difficult to get to the proper plane of analysis. Thus, it will be increasingly important to understand not only the cutting-edge techniques, but also the limitations of each technique provided by the remaining structure. Please join us for a survey of seven different defect localisation techniques, which are based on ion, electron, X-ray, and acoustic beams or sources.

Greg Johnson – Senior Applications Development Engineer, ZEISS Microscopy

Greg worked for eight years in the Advanced Packaging Laboratory of IBM Microelectronics. He was also a manufacturing sector leader in the Bond, Assembly, and Test line of IBM before joining the Semiconductor Research and Development Centre, where he developed new defect localisation techniques in laser and electron-beam based techniques across eight successful technology node qualifications. He is listed as inventor on 19 U.S. Patents. He is now a Senior Application Development Engineer in the Electronics group of ZEISS Microscopy.

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Date/Time
Date(s) - 23/10/2020
12:00 pm - 1:00 pm

Location
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